Method for manufacturing semiconductor device using plasma-enhanced atomic layer deposition

ABSTRACT

A method for manufacturing a semiconductor device using a plasma-enhanced atomic layer deposition is provided. A substrate comprising a silicon substrate and a first oxide layer is provided. Stacked structures are deposited on the substrate, which comprises a dielectric layer and a conductive layer. The stacked structures are etched to form at least one trench. A second oxide layer is deposited on the stacked structures and the trench using a plasma-enhanced atomic layer deposition apparatus includes a chamber, an upper electrode including nozzles, and a lower electrode. The upper electrode is connected to a first radio-frequency power device configured to generate plasma and a second radio-frequency power device configured to clean the nozzles. The lower electrode is connected to a third radio-frequency power device. A high resistance layer is deposited on the second oxide layer and a low resistance layer is deposited on the high resistance layer.

FIELD OF THE INVENTION

The present disclosure relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device by a plasma-enhanced atomic layer deposition.

BACKGROUND OF THE INVENTION

The semiconductor industry is constantly booming. Technological advances in semiconductor design and materials have resulted in smaller and more complex circuits for semiconductor devices. The functional density of semiconductor devices is generally increased and the size is reduced, which can increase production efficiency and reduce costs.

The functionality of semiconductor devices is limited by the area of the semiconductor wafer, and as semiconductor technology advances, more and more devices employ three-dimensional stacking techniques to increase the density of components. However, three-dimensional stacking techniques increase the complexity of semiconductor device processing and make it more difficult to maintain the process quality and stability of semiconductor devices and affect yield. Semiconductor wafers for three-dimensional integrated circuits have high structural and process requirements. Existing three-dimensional semiconductor processes still have a number of problems that affect the electrical and mechanical properties of semiconductor wafers. Therefore, a corresponding development in the fabrication of semiconductor devices to improve the quality and stability of the fabrication process is urgently needed.

SUMMARY OF THE INVENTION

The present disclosure provides a method for fabricating a semiconductor device using a plasma-enhanced atomic layer deposition that can substantially improve the uniformity of the deposited film.

Another aspect of the present disclosure is to provide a semiconductor device capable of greatly improving the uniformity of a deposited film.

In an embodiment, a method for manufacturing a semiconductor device by a plasma-enhanced atomic layer deposition of the present disclosure comprises the following steps. A substrate comprising a silicon substrate and a first oxide layer on the silicon substrate is provided. A plurality of stacked structures are deposited on the substrate, wherein each of the plurality of stacked structures comprises a dielectric layer and a conductive layer. The stacked structures are etched through a patterned photoresist layer to form at least one trench in the stacked structures, wherein the first oxide layer is exposed at a bottom of the trench. A second oxide layer is deposited on the stacked structures and the trench by a plasma-enhanced atomic layer deposition apparatus, wherein the plasma-enhanced atomic layer deposition apparatus comprises a chamber, an upper electrode and a lower electrode, the upper electrode is arranged at a top of the chamber and connected to a first radio-frequency power device and a second radio-frequency power device, the upper electrode comprises a plurality of nozzles, the first radio-frequency power device is configured for the nozzles of the upper electrode to generate a plasma, the second radio-frequency power device is configured for cleaning the nozzles, the lower electrode is arranged at a bottom of the chamber and is connected to a third radio-frequency power device, the substrate is arranged on the lower electrode to perform a deposition process. a high resistance layer is deposited on the second oxide layer by the plasma-enhanced atomic layer deposition apparatus. A low resistance layer is deposited on the high resistance layer by the plasma-enhanced atomic layer deposition apparatus.

In an embodiment, a semiconductor device of the present disclosure comprises a substrate, a plurality of stacked structures, at least one trench, a second oxide layer, a high resistance layer and a low resistance layer. The substrate comprises a silicon substrate and a first oxide layer on the silicon substrate. The stacked structures are deposited on the substrate, wherein each of the stacked structures comprises a dielectric layer and a conductive layer. The trench is formed by etching the stacked structures through a patterned photoresist layer. The first oxide layer is exposed at a bottom of the trench. The second oxide layer is deposited on the stacked structures and the trench, wherein the second oxide layer is deposited by a plasma-enhanced atomic layer deposition apparatus, the plasma-enhanced atomic layer deposition apparatus comprises a chamber, an upper electrode and a lower electrode, the upper electrode is arranged at a top of the chamber and connected to a first radio-frequency power device and a second radio-frequency power device, the upper electrode comprises a plurality of nozzles, the first radio-frequency power device is configured for the nozzles of the upper electrode to generate a plasma, the second radio-frequency power device is configured for cleaning the plurality of nozzles, the lower electrode is arranged at a bottom of the chamber and connected to a third radio-frequency power device, the substrate is arranged on the lower electrode to perform a deposition process. The high resistance layer is deposited on the second oxide layer by the plasma-enhanced atomic layer deposition apparatus. The low resistance layer is deposited on the high resistance layer by the plasma-enhanced atomic layer deposition apparatus.

The present disclosure provides a semiconductor device and a manufacturing method thereof, by providing a plurality of stacked structures, a second oxide layer, a high-resistance layer, and a low-resistance layer, the quality and stability of the semiconductor device can be greatly improved. By providing a plurality of nozzles on the upper electrode of the plasma-enhanced atomic layer deposition apparatus, an uniform and stable plasma can be generated and the nozzles can be cleaned. As a result, the plasma-enhanced atomic layer deposition apparatus can greatly improve the uniformity of the deposited film.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1, FIG. 2, FIG. 3, and FIG. 4 are cross-sectional views illustrating intermediate stages of a process of a method for fabricating a semiconductor device using a plasma-enhanced atomic layer deposition according to some embodiments.

FIG. 5 is a schematic diagram of a semiconductor device according to an embodiment of the present disclosure.

FIG. 6 is a schematic diagram of a plasma-enhanced atomic layer deposition apparatus according to an embodiment of the present disclosure.

FIG. 7A is a partial schematic diagram of a plasma-enhanced atomic layer deposition apparatus according to an embodiment of the present disclosure.

FIG. 7B is a partial schematic diagram of a plasma-enhanced atomic layer deposition apparatus according to an embodiment of the present disclosure.

FIG. 8 is a flowchart of a method for fabricating a semiconductor device using a plasma-enhanced atomic layer deposition according to an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Directional terms mentioned in the following embodiments, for example: up, down, left, right, front, or back, etc. refer only to the directions of the attached drawings. Therefore, directional terms are used to describe and not to limit the disclosure.

As used herein, the terms “about”, “approximately”, and “substantially” typically mean within +/−20% of a given value, more typically within +/−10% of a given value, more typically within +/−5% of a given value, more typically within 3% of a given value, more typically within +/−2% of a given value, more typically within +/−1% of a given value, and even more typically within +/−0.5% of a given value. The numerical values given in this disclosure are approximate numerical values, i.e. the values given can still have the meaning of “about” or “substantially” without being specifically stated with the terms “about” or “substantially”.

With reference to FIG. 1, FIG. 2, FIG. 3, FIG. 4, and FIG. 5, FIG. 1, FIG. 2, FIG. 3, and FIG. 4 are cross-sectional views of intermediate stages in a method for manufacturing a semiconductor device using a plasma-enhanced atomic layer deposition according to some embodiments. FIG. 5 is a schematic diagram of a semiconductor device 1 according to an embodiment of the present disclosure.

Referring to FIG. 1, a substrate 11 which comprises a silicon substrate 111 and a first oxide layer 113 on the silicon substrate 111 is provided in step S101.

Referring to FIG. 2, in step S103, a plurality of stacked structures 13 a, 13 b, 13 c are disposed on the substrate 11. Each of the stacked structures 13 a, 13 b, 13 c comprises a dielectric layer and a conductive layer. FIG. 2 illustrates that the deposition of three of the stacked structures 13 a, 13 b, 13 c, and one of the stacked structure 13 a in which comprises a dielectric layer 133 and a conductive layer 131. The number of stacked structures in the present disclosure is not limited thereto. In the present embodiment, the dielectric layer 133 is positioned above the conductive layer 131 in one of stacked structures 13 a, 13 b, 13 c, but the present disclosure is not limited thereto. In other embodiments of the present disclosure, the conductive layer 131 is positioned above the dielectric layer 133 in one of the stacked structures 13 a, 13 b, 13 c.

In one embodiment of the present disclosure, a number of stacked structures 13 a, 13 b, 13 c of the semiconductor device is greater than twenty. In each of the stacked structures 13 a, 13 b, 13 c, the dielectric layer 133 is arranged above the conductive layer 131. Alternatively, the conductive layer 131 is arranged above the dielectric layer 133.

Referring to FIG. 3, the stacked structures 13 a, 13 b, 13 c are etched through a patterned photoresist layer PR to perform an etching process E in step S105. Referring to FIG. 4, also in step S105, at least one trench t is formed in the stacked structures 13 a, 13 b, 13 c during the etching process E, wherein the first oxide layer 113 is exposed at a bottom of the trench t. For convenience of explanation, FIG. 4 takes only one such trench t for an example, but the number of trenches in the present disclosure is not limited thereto.

Reference is first made to FIG. 6, a schematic diagram of a plasma-enhanced atomic layer deposition (PEALD) apparatus 20, according to an embodiment of the present disclosure. The plasma-enhanced atomic layer deposition apparatus 20 includes a chamber 21, an upper electrode 23 and a lower electrode 25. The upper electrode 23 is arranged at a top of the chamber 21 and is connected to a first radio-frequency power device 24 a and a second radio-frequency power device 24 b.

FIG. 7A shows a partial schematic diagram of a plasma-enhanced atomic layer deposition apparatus 20 according to an embodiment of the present disclosure. The upper electrode 23 of the plasma-enhanced atomic layer deposition apparatus 20 further includes a plurality of nozzles 231. The first radio-frequency power device 24 a is provided for the plurality of nozzles 231 of the upper electrode 23 to generate a plasma P. The second radio-frequency power device 24 b is provided for cleaning the plurality of nozzles 231. The lower electrode 25 is arranged at a bottom of the chamber 21 and is connected to a third radio-frequency power device 26, and the substrate 11 is placed on the lower electrode 25 to perform a deposition process D. The substrate 11 shown in FIG. 6 is only for illustration but the disclosure is not limited thereto.

In step S107, referring to FIG. 5, a second oxide layer 15 is deposited on the stacked structures 13 a, 13 b, 13 c and the trench t by the plasma-enhanced atomic layer deposition apparatus 20 shown in FIG. 6. In step S109, a high resistance layer 17 is deposited on the second oxide layer 15 by the plasma-enhanced atomic layer deposition apparatus 20 as shown in FIG. 6.

Next, in step S111, a low resistance layer 19 is deposited on the high resistance layer 17 by the plasma-enhanced atomic layer deposition apparatus 20 shown in FIG. 6. The plasma P can be uniformly and stably generated by providing the plurality of nozzles 231 on the upper electrode 23, and the uniformity of a deposited film can be greatly improved. The upper electrode 23 is capable of cleaning the plurality of nozzles 231. Thus, the plasma-enhanced atomic layer deposition apparatus 20 can substantially improve the uniformity of the deposited film.

In this embodiment, the lower electrode 25 facilitates the deposited film formed in a deep trench. The plasma P generated by the upper electrode 23 can be deposited deeper into the trench t by virtue of the lower electrode 25. Thereby, the uniformity of the deposited film can be greatly improved.

In one embodiment of the present disclosure, the high resistance layer 17 includes a first polysilicon layer 171 and a first conductive compound layer 173, but the present disclosure is not limited thereto. In one embodiment of the present disclosure, the first conductive compound layer 173 is arranged above the first polysilicon layer 171.

In one embodiment of the present disclosure, the low resistance layer 19 includes a second polysilicon layer 191 and a second conductive compound layer 193, although the present disclosure is not limited thereto. In one embodiment of the present disclosure, the second conductive compound layer 193 is arranged above the second polysilicon layer 191.

In one embodiment of the present disclosure, the second polysilicon layer 191 has a thickness greater than the first polysilicon layer 171 and the second conductive compound layer 193 has a thickness greater than the first conductive compound layer 173, although the present disclosure is not limited thereto.

As shown in FIG. 7A, in detail, each of the nozzles 231 comprises a slot h. The slot h extends from an upper surface of the upper electrode 23 to a lower surface of the upper electrode 23. An opening of the slot h on the upper surface is an upper opening 2311 and an opening of the slot h on the lower surface is a lower opening 2313. In an embodiment of the present disclosure, the lower opening 2313 is larger than the upper opening 2311, and the slot h is tapered from the lower opening 2313 to the upper opening 2311. In particular, the slot h may be, for example, in the shape of a horn at the lower opening 2313. Thereby, the upper electrode 23 of the plasma-enhanced atomic layer deposition apparatus 20 can generate the plasma P uniformly and stably through the nozzles 231, and the uniformity of the deposited film can be greatly improved.

FIG. 7B shows a partial schematic diagram of a plasma-enhanced atomic layer deposition apparatus according to an embodiment of the present disclosure. In an embodiment of the present disclosure, a profile of the lower opening 2313 is a hexagon. Thereby, the upper electrode 23 of the plasma-enhanced atomic layer deposition apparatus 20 can generate the plasma P uniformly and stably through the arrangement of the nozzles 231, and the uniformity of the deposited film can be greatly improved. In an embodiment of the present disclosure, the profile of the lower opening 2313 is a regular hexagon.

In addition, the plasma-enhanced atomic layer deposition apparatus 20 may, for example, further comprise a three-dimensional rotation device 27. The three-dimensional rotation device 27 is disposed below the chamber 21. The lower electrode 25 is arranged at the bottom of the three-dimensional rotating device 27. During the deposition process D, the substrate is rotated by the three-dimensional rotation device 27 to be uniformly deposited. Through the three-dimensional rotation device 27, the plasma-enhanced atomic layer deposition apparatus 20 can greatly improve the uniformity of the deposited film.

The deeper the at least one trench t is, the more difficult it is to be deposited. That is, it is difficult for the plasma P generated by the upper electrode 23 to perform a deposition process for a region on the sidewall of the deep trench t. Through the three-dimensional rotation device 27, the substrate 11 is rotated during the above-mentioned deposition processes, so that the region on the sidewall of the deep trench t can be more uniformly deposited. Thereby, the uniformity of the deposited film can be greatly improved.

As shown in FIG. 6, in detail, a direction from the lower electrode 25 to the upper electrode 23 of the plasma-enhanced atomic layer deposition apparatus 20 is a first direction D1. If the three-dimensional rotation device 27 does not rotate, a normal direction N of the substrate 11 is parallel to the first direction D1. If the three-dimensional rotation device 27 drives the substrate 11 to rotate, the normal direction of the substrate 11 forms an angle A with the first direction D1. In the present embodiment, the angle A is between 0 degree and 15 degrees. Thus, the plasma-enhanced atomic layer deposition apparatus 20 can substantially improve the uniformity of the deposited film.

In one embodiment of the present disclosure, the upper electrode 23 is connected to an upper heater 233. In the deposition processes D described above, the upper heater 233 heats the upper electrode 23 to facilitate uniform deposition. As a result, the plasma-enhanced atomic layer deposition apparatus 20 can substantially improve the uniformity of the deposited film.

In one embodiment of the present disclosure, the lower electrode 25 is connected to a lower heater 251. In each of the deposition processes D described above, the lower heater 251 heats the lower electrode 25 to facilitate uniform deposition. As a result, the plasma-enhanced atomic layer deposition apparatus 20 can substantially improve the uniformity of the deposited film.

In this embodiment, the second polysilicon layer 191 has a thickness greater than the first polysilicon layer 171 and the second conductive compound layer 193 has a thickness greater than the first conductive compound layer 173. Specifically, a resistance of the high resistance layer 17 is higher than that of the low resistance layer 19. By the arrangement of the stacked structures 13 a, 13 b, 13 c, the second oxide layer 15, the high resistance layer 17, and the low resistance layer 19, the quality and stability of the semiconductor device 1 can be greatly improved.

In one embodiment of the present disclosure, the thickness of the second conductive compound layer 193 is between 20 nm and 50 nm.

As shown in FIG. 5, after the low resistance layer 19 is deposited in step S111, a trench t1 still exists in the trench t, but the present disclosure is not limited thereto. In other embodiments of the present disclosure, after depositing the low resistance layer 19, the low resistance layer 19 may fill in the at least one trench t, i.e. there is no trench t1 as shown in FIG. 5.

In one embodiment of the present disclosure, the conductive layer of the stacked structures 13 a, 13 b, 13 c is a P-type semiconductor layer or an N-type semiconductor layer and the dielectric layer is an oxide layer. For example, the conductive layer 131 of one of the plurality of the stack layer 13 a is a P-type semiconductor layer or an N-type semiconductor layer, and the dielectric layer 133 is an oxide layer.

In one embodiment of the present disclosure, a material of the first conductive compound layer 173 and/or the second conductive compound layer 193 may be BN, BP, BAs, AlN, AlP, AlAs, GaN, GaP, GaAs, InN, InP, InAs or a combination of at least two of the above-mentioned.

In one embodiment of the present disclosure, a conductivity of the high resistance layer 17 is about 1e15 S·m⁻¹ and a conductivity of the low resistance layer 19 is about 1e20 S·m⁻¹. The thickness of the high resistance layer 17 is about 20 nm, and the thickness of the low-resistance layer 19 is about 30 nm.

As shown in FIG. 4, in one embodiment of the present disclosure, a width w of the trench t is between 45 nm and 65 nm. A thickness of the silicon substrate 111 of the substrate 11 is between 520 nm and 580 nm, and a thickness the first oxide layer 113 is between 90 nm and 110 nm. In the plurality of stacked structures 13 a, 13 b, 13 c (exemplified by the stacked structure 13 a), a thickness of the dielectric layer 133 is between 18 nm and 22 nm, and a thickness of the conductive layer 131 is between 27 nm and 33 nm.

FIG. 8 shows a flowchart illustrating a method for manufacturing the plasma enhanced atomic layer deposition device 20 according to an embodiment of the present disclosure. Specifically, FIG. 7 is a flowchart of a manufacturing method 100 of the semiconductor device 1 shown in FIG. 5. Multiple implementation details of the steps S101, S103, S105, S107, S109, and S111 included in the manufacturing method 100 are described in detail in the foregoing embodiments and implementations, and will not be described in detail below.

In view of the above-mentioned content, the semiconductor device and the manufacturing method thereof according to the embodiments of the present disclosure can significantly improve the quality and stability of the semiconductor device by providing the plurality of stacked structures, the second oxide layer, the high resistance layer, and the low resistance layer. By providing a plurality of nozzles on the upper electrode of the plasma-enhanced atomic layer deposition apparatus, a uniform and stable plasma can be generated and the nozzles can be cleaned. As a result, the plasma-enhanced atomic layer deposition apparatus can greatly improve the uniformity of the deposited film. 

What is claimed is:
 1. A method for fabricating a semiconductor device using a plasma-enhanced atomic layer deposition, comprising: providing a substrate which comprises a silicon substrate and a first oxide layer on the silicon substrate; depositing a plurality of stacked structures on the substrate, wherein each of the stacked structures comprises a dielectric layer and a conductive layer; etching the stacked structures through a patterned photoresist layer to form at least one trench in the stacked structures, wherein the first oxide layer is exposed at a bottom of the at least one trench; depositing a second oxide layer on the stacked structures and the trench by a plasma-enhanced atomic layer deposition apparatus, wherein the plasma-enhanced atomic layer deposition apparatus comprises a chamber, an upper electrode and a lower electrode, the upper electrode is arranged at a top of the chamber and connected to a first radio-frequency power device and a second radio-frequency power device, the upper electrode comprises a plurality of nozzles, the first radio-frequency power device is configured for the nozzles of the upper electrode to generate a plasma, the second radio-frequency power device is configured for cleaning the nozzles, the lower electrode is arranged at a bottom of the chamber and is connected to a third radio-frequency power device, the substrate is arranged on the lower electrode to perform a deposition process; depositing a high resistance layer on the second oxide layer by the plasma-enhanced atomic layer deposition apparatus; and depositing a low resistance layer on the high resistance layer by the plasma-enhanced atomic layer deposition apparatus.
 2. The method of claim 1, wherein each of the nozzles comprises a slot that extends from an upper surface of the upper electrode to a lower surface of the upper electrode.
 3. The method of claim 2, wherein an upper opening of the slot in the upper surface is larger than a lower opening of the slot in the lower surface, and the slot is tapered from the lower opening to the upper opening.
 4. The method of claim 2, wherein a profile of a lower opening of the slot in the lower surface is a hexagon.
 5. The method of claim 1, wherein the plasma-enhanced atomic layer deposition apparatus further comprises a three-dimensional rotation device that is disposed below the chamber, the lower electrode is arranged at the bottom of the three-dimensional rotation device, and the substrate is rotated by the three-dimensional rotation device during the deposition process to achieve uniform deposition.
 6. The method of claim 5, wherein a direction from the lower electrode to the upper electrode is a first direction, if the three-dimensional rotation device does not rotate, a normal direction of the substrate is parallel to the first direction, and if the three-dimensional rotation device drives the substrate to rotate, the normal direction of the substrate comprises an angle with the first direction, the angle is between 0 degree and 15 degrees.
 7. The method of claim 1, wherein the upper electrode is connected to an upper heater such that the upper electrode is heated during the deposition process to achieve uniform deposition.
 8. The method of claim 1, wherein the lower electrode is connected to a lower heater such that the lower electrode is heated during the deposition process to achieve uniform deposition.
 9. The method of claim 1, wherein the high resistance layer comprises a first polysilicon layer and a first conductive compound layer, the low resistance layer comprises a second polysilicon layer and a second conductive compound layer, the second polysilicon layer has a thickness greater than the first polysilicon layer, and the second conductive compound layer has a thickness greater than the first conductive compound layer.
 10. The method of claim 1, wherein a number of the stacked structures is greater than twenty, and the dielectric layer is arranged above or below the conductive layer in each of the stacked structures.
 11. The method of claim 1, wherein the conductive layer is a P-type semiconductor layer or an N-type semiconductor layer and the dielectric layer is an oxide layer.
 12. The method of claim 1, wherein a width of the trench is between 45 nm and 65 nm.
 13. The method of claim 1, wherein a thickness of the silicon substrate is between 520 nm and 580 nm, a thickness of the first oxide layer is between 90 nm and 110 nm, a thickness of the dielectric layer is between 18 nm and 22 nm, and a thickness of the conductive layer is between 27 nm and 33 nm. 